Showing posts with label flip flop. Show all posts
Showing posts with label flip flop. Show all posts

How To Avoid Race Around Condition in JK Flip Flop

  Race around condition is the most important condition in Digital electronics. In J-K Flip flop, when J=K=1 the output changes its state. When a clock pulse width tp is applied the output will change from 1 to 0 after a time interval of Δt, where Δt is the propagation delay through two NAND Gates in series. Now after Δt we have J=K=1, Q=0, After another interval of Δt, output Q will become 1. Hence the output will oscillates back and forth between 0 and 1 in the duration tp of the clock pulse width.